1. Field of the Disclosure
This disclosure pertains to analog-to-digital converters (ADCs) and specifically to successive approximation register (SAR)-based ADCs.
2. Description of the Related Art
Successive approximation register (SAR)-based analog-to-digital converters (ADCs) SAR ADCs require several comparison cycles to complete conversion of one sampled analog signal to a digital value, and therefore have limited operational speed. Due to low power consumption, SAR architectures are extensively used in low-power and low-speed applications with a sampling frequency of less than several MSamples/s (MS/s). In recent years, SAR ADCs have achieved sampling rates of several tens of MS/s to low GS/s with 5-bit to 10-bit resolutions in part due to a scaling down of the feature sizes of Complementary Metal Oxide Semiconductor (CMOS).
As the sampling frequency increases, the SAR ADCs have reduced amount of time for digital-to-analog converter (DAC) capacitor network settling. For example, a typical 10-bit 100 MS/s SAR ADC, has less than 0.4 ns in each sampling cycle for DAC capacitor network to settle after accounting for sampling settling time, comparator active time, and SAR logic delay time. Increased interconnect line impedance due to the use of advanced CMOS processes may also slow down charge transfer of the capacitors in SAR ADCs, preventing SAR ADCs to operate at a higher sampling speed.